Thursday, 29 June 2017

Fixing Rx_Core with SERDES primitive for Xilinx 7 Series FPGAs

I have been having trouble in implementing a Serializer and Deserialize (SERDES) primitive with my VHDL Rx_Core Firware for the past few days, which was resolved today. Aparantly for the new Kintex and Virtex 7 series FPGAs they have updated their primitives to handle more incoming data. Earlier mine was a 4 bit, I had to replace it with a new one of 8-bits, thus, grounding the higher order bits.
more info on the same can be found in the application note by Xilinx: LVDS Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication

Xilinx Primitives are components that can be implemented in our HDL. They are defined in the UNISIM library.

Next challenge that appears in the vicinity is fixing the clock multiplication problem to run our Rx_Core. Timon had just now suggested me to look into PLLs to achieve this. I also have help from Daniel from University of Valencia, Spain who is working on the gigabit transceiver (GBT) framework for optical communication. So, we can get going now!

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